Regviz

Nordic Semiconductor /nrf52 /MWU /INTENCLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTENCLR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Nordic Semiconductor/nrf52/MWU/INTENCLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)REGION0WA 0 (Disabled)REGION0RA 0 (Disabled)REGION1WA 0 (Disabled)REGION1RA 0 (Disabled)REGION2WA 0 (Disabled)REGION2RA 0 (Disabled)REGION3WA 0 (Disabled)REGION3RA 0 (Disabled)PREGION0WA 0 (Disabled)PREGION0RA 0 (Disabled)PREGION1WA 0 (Disabled)PREGION1RA

REGION1WA=Disabled, PREGION1RA=Disabled, REGION0RA=Disabled, REGION0WA=Disabled, PREGION0RA=Disabled, REGION3RA=Disabled, REGION3WA=Disabled, PREGION0WA=Disabled, PREGION1WA=Disabled, REGION2WA=Disabled, REGION2RA=Disabled, REGION1RA=Disabled

Description

Disable interrupt

Fields

REGION0WA

Write ‘1’ to Disable interrupt for REGION[0].WA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
REGION0RA

Write ‘1’ to Disable interrupt for REGION[0].RA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
REGION1WA

Write ‘1’ to Disable interrupt for REGION[1].WA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
REGION1RA

Write ‘1’ to Disable interrupt for REGION[1].RA event

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
REGION2WA

Write ‘1’ to Disable interrupt for REGION[2].WA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
REGION2RA

Write ‘1’ to Disable interrupt for REGION[2].RA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
REGION3WA

Write ‘1’ to Disable interrupt for REGION[3].WA event

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
REGION3RA

Write ‘1’ to Disable interrupt for REGION[3].RA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PREGION0WA

Write ‘1’ to Disable interrupt for PREGION[0].WA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PREGION0RA

Write ‘1’ to Disable interrupt for PREGION[0].RA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PREGION1WA

Write ‘1’ to Disable interrupt for PREGION[1].WA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PREGION1RA

Write ‘1’ to Disable interrupt for PREGION[1].RA event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled

Links

()

Register License

Copyright © 2010 - 2021, Nordic Semiconductor ASA All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data